A Methodology for Modeling a Complex Geometry on Wafer from a Layout Data

This paper reports a novel methodology and its application to the modeling of a complex 3D geometry on wafer from a layout data. Our modeling method comprises the steps of: drawing a mask layout; transforming the mask layout into a 3D structure by simulating the physical semiconductor process; and extracting device parameters by numerical technique. In order to estimate a 3D structure from the mask layout data, we performed a topography simulation comprising various depositions and etching process steps. A finite element method (FEM) has been employed for extracting device parameters in the 3D structure such as a cell capacitor and interlayer dielectric. A concave cylindrical DRAM cell capacitor with a minimum feature size of 0.25 μm was chosen as a test vehicle to check the validity of the simulation. In this work, 62 parasitic capacitance with 4 cell-capacitance were extracted from a stacked DRAM cell structure over a bit line.